(delivery 6) Well Counters
continue with the examples in vhdl today 3 examples I bring more to complete our progress. the next delivery will become more interesting. You started a project in vhdl
.
Example 19: Designing in VHDL, a 4-bit counter. Falling edge.
Solution: As clock'EVENT AND falling edge clock = '0 '(we can tb Use rising edge). . Also for convenience and to observe, we used the integer data type (so integer) for output, I mean if we vhdl 0 to 15 then automatically generate an output of 4 bits representing the binary numbers from 0 to 15. Now if we
Integer range 0 to 26 say
some value, then the program automatically generates 5-bit output to represent these numbers.
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- Counter 4-bit binary up. -------------------------------------------------
- ENTITY contador_4bits
IS PORT (clock, reset: IN BIT;
out: OUT INTEGER RANGE 0 TO 15);
conta_rs END;
IS ARCHITECTURE rtl OF contador_4bits
BEGIN PROCESS (clock, reset) VARIABLE
account : INTEGER RANGE 0 TO 15;
BEGIN IF (reset = '1 ') THEN
account: = 0;
ELSIF (clock'EVENT AND clock = '0') THEN
account: = count +1;
END IF ;
output \u0026lt;= count;
END PROCESS;
END rtl;
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Example 20: Designing in VHDL, an up counter declining 4 bits.
Solution: ---------------------------------- -----------------
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- descending ascending binary counter - 4 bits. -------------------------------------------------
- ENTITY Contador_asc_desc
IS PORT (clock, enable, asc_des: IN BIT;
out: OUT INTEGER RANGE 0 TO 15);
Contador_asc_desc END;
ARCHITECTURE rtl OF Contador_asc_desc IS BEGIN
PROCESS (clock) VARIABLE
account: INTEGER RANGE 0 TO 15;
BEGIN IF (clock'EVENT AND clock = '0 ') THEN
IF (enable =' 1 'AND asc_des = '1') THEN
account: = count +1;
ELSIF (enable = '1 'AND asc_des = '0') THEN
account: = count-1;
END IF;
END IF;
output \u0026lt;= count;
END PROCESS;
END rtl;
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Example 21: Designing in VHDL, an 8-bit up counter.
Solution: In this code, as we vary the type of variable output in the above examples was integer, but let's see what happens when it is represented as a vector of 7 downto 0. Then tell them nothing happens from now is treated the same sum 1 (or subtract if it can also down). We used a rising edge to falling edge, in addition to make it more interesting was an enabler (enable) to start or not the account.
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- Binary Counter ascending descending - 4 bits.
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library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY contador8bits more
port (
; couto: out std_logic_vector (7 downto 0);
enable :in std_logic;
clk :in std_logic;
reset :in std_logic
);
end contador8bits;
architecture rtl of contador8bits is
signal count :std_logic_vector (7 downto 0);
begin
process (clk, reset) begin
if (reset = '1') then
count <= (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
count <= count + 1;
end if;
end if;
end process;
cout <= count;
end rtl;
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Now all the above examples are theoretically well when implemented, but really this does not happen when one writes these codes on the cards fpga, because the output does not see absolutely no account, and this going by the clock that we use. When I tuilize
FPGA cards facu .. defined just as the clock input of our program counter, an external input clock of the card. however if you do not want to use the external input and want to use the FPGA's internal oscillator, m using a crossover
(seen before), then wait for the next delivery which use the clock of 1 Hz + a counter them.
But of course, tell them they can use a structured description
defic leg clock output of 1 Hz as the clock input of our counter.
