vhdl examples (part 7) Laboratory reports penultimate Good day ... I hope you super fence ... well this is our penultimate delivery of basic examples in VHDL
would fail only perform sequential machines mealy and moore ... the last delivery of these examples show .. they are relatively simple, well-placed only with the clock event (rising edge) ...
Example 22: Designing in VHDL, a 4-bit up counter with 1Hz clock.
Solution: example published in
http://www.todopic.com.ar
--------------------------------- -------------------------------------------------- -
- 4 bit up counter with 1 Hz clock
- Author: Americo Alvarez S.
- Date: March 5, 2011
- Module Name: counter_4b_1hz
- Description:
- After seeing the great disadvantage of the clock
- - had the counters when
implement - in fpga card. We saw the need to implement
- a counter with frequency f = 1Hz.
- The output is the binary observed in LEDs.
- Abstract:
-
- Vercion: vercion 0
- -------------------------------------------------- --------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
IEEE.STD_LOGIC_ARITH use. ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY
counter_4b_1hz is
Port (clock_50Mhz: in Std_logic; reset: in bit;
F: OUT INTEGER RANGE 0 TO 15);
counter_4b_1Hz END;
counter_4b_1hz
ARCHITECTURE rtl OF SIGNAL IS
clkout: std_logic;
CONSTANT max: INTEGER: = 50000000;
CONSTANT half: INTEGER: = max / 2;
SIGNAL count: INTEGER RANGE 0 TO max;
BEGIN
- 1Hz clock signal generating frequency
PROCESS BEGIN WAIT
UNTIL clock_50Mhz'EVENT and clock_50Mhz = '1';
IF count < max THEN count <= count + 1;
ELSE count <= 0;
END IF;
IF count < half THEN clkout <= '0';
ELSE clkout <= '1';
END IF;
END PROCESS;
--contador 4 bits ascendente
PROCESS(clkout,reset)
VARIABLE cuenta: INTEGER RANGE 0 TO 15;
BEGIN
IF (reset='1') THEN
cuenta:=0;
ELSIF (Clkout'EVENT AND clkout = '0 ') THEN
account: = count +1;
END IF;
F \u0026lt;= count;
END PROCESS;
END rtl ;
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Example 23: Designing in VHDL, a 4-bit up counter with 1Hz clock, which displays output in hexadecimal number 7-segment display
Solution: -------------------------------------- -------------------------------------------------- -
- 4 bit up counter with 1 Hz clock,
- leaving hexadecimal 7 segment display
- Author: Americo Alvarez S.
- Date: March 25, 2011
- Module Name: counter_4b_7seg
- Description:
- After seeing the great disadvantage of the clock
- - had the counters when
implement - in the FPGA board. We saw the need to implement
- a Counter with frequency f = 1Hz.
- The output is observed in hexadecimal display 7SEG.
- Abstract:
-
- Vercion: -----------------------------------------------
vercion 0.1 -------------------------------------------
library IEEE;
use IEEE . STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY
counter_4b_7seg is
Port (clock_50Mhz: in std_logic; reset: in bit;
; 7SEG: OUT STD_LOGIC_VECTOR (7 downto 0);
END counter_4b_7seg;
ARCHITECTURE rtl OF counter_4b_1hz IS
SIGNAL clkout: std_logic;
CONSTANT max: INTEGER := 50000000;
CONSTANT half: INTEGER := max/2;
SIGNAL count: INTEGER RANGE 0 TO max;
SIGNAL F: INTEGER RANGE 0 to 15
BEGIN
-- generando señal clock de 1Hz de frecuencia
PROCESS
BEGIN
WAIT UNTIL clock_50Mhz'EVENT and clock_50Mhz = '1';
IF count < max THEN count <= count + 1;
ELSE count <= 0;
END IF;
IF count < half THEN clkout <= '0';
ELSE clkout <= '1';
END IF;
END PROCESS;
--contador 4 bits ascendente
PROCESS(clkout,reset)
VARIABLE cuenta: INTEGER RANGE 0 TO 15;
BEGIN
IF (reset='1') THEN
cuenta:=0;
ELSIF (clkout'EVENT AND clkout='0') THEN
cuenta:=cuenta+1;
END IF;
F <= cuenta;
BEGIN
case F is
when 0 => 7SEG :="10000001";
when 1 => 7SEG :="11001111";
when 2 => 7SEG :="10010010";
when 3 => 7SEG :="10000110";
when 4 => 7SEG :="11001100";
when 5 => 7SEG :="10100100";
when 6 => 7SEG :="11100000";
when 7 => 7SEG :="10001111";
when 8 => 7SEG :="10000000";
when 9 => 7SEG :="10000100";
when 10 => 7SEG :="11100010";
when 11 => 7SEG :="11100000";
when 12 => 7SEG :="11110010";
when 13 => 7SEG :="11000010";
when 14 => 7SEG :="10110000";
when 15 => 7SEG :="10111000";
When Others => null;
case
end END PROCESS;
END rtl;
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Well hope to be of show digital clock and timer, but will not be possible to finish the semester and I have no time ... a very helpful suggestion, if you can not design in vhdl leguaje the easiest way to present the work in laboratories simulation is to capture or schematic using quartus2 WebPack xilinx ise because simulators are schematic capture all basic components for any digital work and is only grasping the component and connecting cables or proteus as
multisim
