16 positions at different frequencies in VHDL Final Projects
matter ETN601 Electronica Digital 1 , we were asked a series of projects to do in fpga, using cards the Cyclone2 facu Altera.
Well, the vast majority of students only use the Quartus schematic capture mode and pulling pre-built components (7490, 7483.7408, etc etc) carried out their projects did not use VHDL PEROOOOOOO that was the objective of the project, according to the projects I did not qualify in vhdl, but a few.
Well, students have great difficulty even with the VHDL language, and this was noted in the final draft, one of the major drawbacks was the CLOCK students who failed as a "program" in vhdl, some were designed and used the external clock idea, to get 1Hz (1 second to clock) and others simply used dela Pushbutton fpga.
Well this time I want to share with you 2 different crossovers do something similar sentences.
Example 17: Designing in VHDL, a clock of 1Hz (1 second), then use for a digital clock.
Solution: The DE2 board includes 2 oscillators that produce clock signals of 27 MHz and 50 MHz. The card also includes an SMA connector used to connect an external clock card
will use the 50Mhz internal clock of the card using VHDL to obtain an output frequency of 1Hz
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- mail-etn.blogspot.com -------------------------------------------------
-
- Author: Americo Alvarez S.
- Description: 1Hz clock, using in-
clock - nal of 50Mhz of Cyclone2 fpga. -------------------------------------------------
-
LIBRARY IEEE;
IEEE.STD_LOGIC_1164.ALL USE, USE
IEEE.STD_LOGIC_ARITH.ALL;
ENTITY delay_clock IS
PORT (
Clk50Mhz: IN STD_LOGIC;
Clk: OUT STD_LOGIC
);
END delay_clock;
ARCHITECTURE rtl OF delay_clock IS
CONSTANT max: INTEGER := 50000000;
CONSTANT half: INTEGER := max/2;
SIGNAL count: INTEGER RANGE 0 TO max;
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clk50Mhz'EVENT and Clk50Mhz = '1';
IF
count < max THEN count <= count + 1;
ELSE count <= 0;
END IF;
IF
count < half THEN Clk <= '0';
ELSE Clk <= '1';
END IF;
END PROCESS;
END rtl;
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Example 18: Designing in VHDL, a 10hz clock, which has a reset to restart the clock.
Solution: this time using the internal clock of 27Mhz fpga, we will pull an output frequency of 10Hz, use the rising edge statement that as discussed earlier, is the same as clock'event, bone side.
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- mail-etn.blogspot.com
--------------------- ------------------------------
- Author: Americo Alvarez S .
- Description: 10Hz clock, using in-
clock - the internal 27Mhz Cyclone2 fpga. -------------------------------------------------
-
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ck_10hz IS
PORT ( reset : IN STD_LOGIC;
clock_in : IN STD_LOGIC;
clock_out : OUT STD_LOGIC);
END ck_10hz;
ARCHITECTURE rtl OF ck_10hz IS
signal ck_cnt : unsigned(20 downto 0);
signal ck_bit : std_logic;
begin
gen_clock: process (clock_in, reset) is
begin
if (reset = '0') then
ck_cnt <= "000000000000000000000";
ck_bit <= '0';
elsif rising_edge(clock_in) then
if (ck_cnt = 1349999) then
ck_cnt <= "000000000000000000000";
ck_bit <= not ck_bit;
else
ck_cnt <= ck_cnt + 1;
end if;
end if;
end process;
clock_out \u0026lt;= ck_bit;
end rtl;
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see in the above examples are 2 ways to perform crossover, using either the internal clock of 50 Mhz and 27Mhz. , also added a reset to stop the clock when we apetesca.
The idea is to use the codes above, was to have packages of clock cycles, for example 50MHz counting the "half" 25Mhz bone marrow that they pass the first 25 million clock cycles is in a state ' 0 'output for the following 25 million is in state 1 output. so we have exactly 1 second.
To make the splitter to 10 Hz was used packages have the same idea of \u200b\u200bclock cycles, having as limit the 27Mhz. bone in 27 MHz would have to divide by 20, 10 cycles '0 'and 10 cycles '1', which would give the 10 hz.
This was the laboratory of electronic No.7 TNC-601 Digital .. I played roulette points and motor PaP. 
